Power supply requirements play an increasingly important role in the design of integrated circuits (ICs). For example, for electronic devices that operate on limited power supplies, such as batteries, the amount of power consumed by the ICs plays a direct role on the amount of time the electronic device can operate before requiring new and/or recharged batteries. The amount of power consumed by an IC is related to the square of the current running through the IC (i.e., P=IV, where V is equal to IR). Thus, when the current is reduced the power is reduced. In addition, some power supplies may be limited by the manner in which they deliver power. For example, while power supplies for electronic devices typically provide power at one voltage, such supplies may have a limited current capability. ICs that require less current provide more flexibility when such current limited supplies are used.
The power consumption of an IC can be reduced by using different device technologies. For example, ICs manufactured with bipolar transistors, while providing rapid switching speeds, have relatively high current requirements. Metal-oxide (insulator)-semiconductor (MOS) transistors can require less power, and in the event complementary MOS (CMOS) technology is employed, substantial power savings can occur. The manner in which CMOS logic devices switch, results in relatively small amounts of current being drawn, and hence consumes less power.
The rate at which an IC draws current also depends upon the operational status of the device (i.e., what function the IC is performing). An IC may be in an "active" state, in which the IC is performing some operation in response to an external signal, or an IC may be in a "stand-by state," in which power is applied to the IC, but the IC is performing minimal functions, or no functions at all. In the active state, an IC will typically draw more current, as its internal devices, such as transistors and the like, are switching between states to arrive at an output signal. Thus, more power is required in the active state. In contrast, IC power consumption can be considerably lower in the stand-by state as few, if any devices are switching between states. Because, in many applications, an IC is in the stand-by state more often than the active state, it is desirable to have the IC draw as little current as possible when in the stand-by state (have a low stand-by current).
Just one example of an IC having an active and stand-by state can be given by the read operation of a random access memory (RAM). Before the read operation, the RAM is in a stand-by state. In response to input signals, such as an address (and/or clock) signal, the RAM enters an active state, and the various internal circuits respond to the input signal by accessing a given memory location and providing the data stored at the location.
The power consumption of an IC can also be reduced by circuit design. The manner in which internal devices switch in relationship to one another can reduce the amount of current required by the IC.
Unfortunately, despite careful selection of device technology and mindful circuit design, there are many uncontrollable factors that result in poor power performance. Among these factors are manufacturing defects created during the fabrication of the IC. Highly integrated semiconductor devices include multiple conductive lines that run over and adjacent to one another, and are separated by insulating layers that can have a thickness in the hundreds of angstroms (.about.500.times.10.sup.-10 m). Thus, a defect in the order of a hundred thousandth of a centimeter can effect the operation of the IC. Defects can arise from any of a number sources: very small particles, variation in starting materials, or lack of precision in a process step--such as an etching step, to name just a few.
Defects arising from manufacturing can be overcome by "repairing" an IC by using redundant circuits. A redundant circuit provides identical functionality to "standard" circuits in an IC. In the event a standard circuit is defective, it can be disabled, and replaced by a redundant circuit. While redundancy can repair an IC so that it is functionally equivalent to a defect free IC, the repaired IC may still consume more power than the defect free IC. As just one example, while a replaced defective standard circuits may never switch between states, the manner of the defect may result in current being drawn. If such an current draw occurs while the IC is in stand-by, the IC can consume an inordinate amount of power.
An example of a defect which causes an IC to continue to draw current in the stand-by state is set forth in FIG. 1. Two conductive lines are illustrated; a first conductive line 100 which is maintained at a first voltage (V1) in the stand-by state, and a second conductive line 102 which is maintained at a second voltage (V2) in the stand-by state. It is understood that V1 is a different potential than V2. If the circuit was defect free, the two conductive lines (100 and 102) would be insulated from one another, and no current could be drawn between the two. A defect 104, however, is illustrated that creates a short circuit condition between the two conductive lines (100 and 102). The short circuit will have some inherent resistance, and so is shown as a m() resistor connecting the two conductive lines (100 and 102). Because V1 is different from V2, current will flow from the higher voltage to the lower voltage through the resistor, consuming power.
A second, more specific example of a defect which can affect power consumption is set forth in FIG. 2a. FIG. 2a illustrates an array of dynamic RAM (DRAM) cells. The array is designated by the reference character 200, and is shown to include fifteen memory cells arranged in six rows and five columns. Each of the memory cells are identified by the character Mij, where i designates a row, and j designates a column. The memory cells M00-M53 are coupled to word lines 202a-202f and bit lines 204a-204f. Each memory cell is show to include an access transistor and storage capacitor, identified by the characters Nij and Cij, respectively, where i and j, again, indicate a row and a column. The storage capacitors C00-C53 are shown to have one terminal coupled to their respective access transistor, and another coupled to a plate terminal 206. The plate terminal 206 is common to each of the memory cells.
In the particular array of FIG. 2a, the various conductive lines are placed at predetermined voltages in the stand-by state. The bit lines 204a-204f are placed at a voltage halfway between a positive supply voltage (Vcc) and a low supply voltage (Vss or ground), and so are shown to be at the potential Vcc/2. This arrangement allows the bit lines 204a-204f to be rapidly driven to either Vcc or Vss in the active cycle. The plate terminal 206 is also placed at Vcc/2. The word lines 202a-202f, on the other hand, are placed at Vss. This ensures that access transistors N00-N53 remain turned off, preventing charge from leaking from the storage capacitors to the bit lines 204a-204f.
Also illustrated in FIG. 2a are two defects; one in memory cell M22 and one in memory cell M40. The first defect 208 in M22 results in a short between the word line 202c and the plate terminal 206. In the stand-by state, current flows through the first defect 208 from the plate terminal 206 (which is at Vcc/2) to the word line 202c (which is at Vss, or zero volts). Similarly, in the vicinity of memory cell M40, the second defect 210 has created a short between bit line 204b and word line 202e. In the stand-by state current flows from the higher potential bit line 204b (at Vcc/2) to the lower potential word line 202e (at Vss).
While the row containing defect 208, and the column containing defect 210 can be replaced by redundant circuits, to provide a functional DRAM device, the defects (208 and 210) will continue to draw current in the stand-by state.
FIG. 2b sets forth a side cross sectional view of a portion of a DRAM device that illustrates two examples of short conditions. The portion of the DRAM is designated by the general reference character 220 and shown to include a trench capacitor type DRAM cell, and to include a word line 222, a bit line 224, and a plate terminal 226. A first short circuit condition 228 is shown between the word line 222 and the plate terminal 226. A second short circuit condition 230 is shown between the word line 222 and the bit line 224.
FIG. 2c provides a second side cross sectional view for a DRAM having a stacked capacitor cell. As in the case of FIG. 2b, two short circuit conditions are illustrated. The portion of the DRAM is designated by the general reference character 240, and includes the same general elements as FIG. 2b. A word line 242 is disposed on a semiconductor substrate adjacent to a bit line 244. A plate terminal 246 is disposed over the word line 242 and below the bit line 244. A first short circuit condition 248 is shown between the plate terminal 246 and the word line 242. A second short circuit condition 250 is shown between the bit line 244 and the word line 242.
Commonly-owned, co-pending U.S. patent application No. 60/064,835 illustrates a method of reducing the amount of current drawn by a memory device in the stand-by state. This application is incorporated by reference herein.
It would be desirable to provide some way of reducing the amount of current that is drawn by a semiconductor device having manufacturing defects, particularly those defects that draw current when the device is in a stand-by state.